With decreasing feature sizes, the need has arisen in the semiconductor integrated circuit industry to move from aluminum (Al) or Al-alloy interconnects to copper (Cu) based metallization layers. Multilevel structures, containing up to 10 levels of Cu interconnect are common in today's devices. Copper has lower resistivity than Al-based alloys, and when used in conjunction with low-k dielectrics, Cu reduces RC interconnect delays. Moreover, Cu-based interconnects exhibit better reliability over Al-based alloys.
The uppermost levels of interconnects typically do not contain low-k dielectrics because of their poor mechanical and chemical stability. These materials have poor strength and low resistance to indentation and shear, and they are inherently brittle. Thus they are unsuitable for wire bonding or flip chip assembly techniques. Therefore, the industry fabricates microelectronic devices with the uppermost (or top two) Cu metallization layers formed within a conventional SiO2-based dielectric. Moreover, the uppermost Cu metal layer has to be passivated with barrier dielectrics such as silicon nitride, silicon dioxide, silicon oxynitride (SiN/SiO2/SiON), or combinations thereof. A conventional semiconductor device 100 is shown in FIG. 1, where a large Cu bond pad 110 is shown as part of a final or outermost Cu interconnect layer that is formed in an outermost dielectric layer 115. Other semiconductors features of the device, such as gates and interconnect layers have been omitted for clarity.
Devices with a large number of I/Os are typically fabricated with flip chip assembly techniques. Since direct bumping to Cu is not commonly available from most commercial assembly operations, it is a commonplace method of fabricating flip chip devices, containing Cu interconnects, to fabricate an Al-alloy bond pad 120 is located over the Cu bond pad 110 in the uppermost level of copper metallization, prior to fabricating the flip chip bump. The Al-alloy bond pad 120 is fabricated subsequent to the formation of a wafer passivation layer 125 that partially covers the Cu bond pad 110, as shown in FIG. 1. A barrier layer (not shown) typically separates the Al-alloy bond pad 120 from the copper bond pad 110. A final passivation layer 130 is deposited thereover. The passivation layer 130 is patterned to allow electrical connection to the Al-alloy bond pad 120. An under bump metallization (UBM) layer 135 is located over the Al-alloy bond pad 120. As is well known in the art, the UBM layer 135 separates the Al-alloy bond pad 120 from a solder bump 140. The Al-alloy bond pad 120 is electrically connected to underlying active components of the semiconductor device through the Cu bond pad 110, which in turn is electrically connected to an underlying interconnect metallization layer (not shown). Thus, as seen from the structure that is shown in FIG. 1, an additional interconnect metallization layer (i.e., the Cu bond pad 110) is required to electrically connect the Al-alloy bond pad 120 with underlying active devices. The fabrication of the Cu bond pad 110 requires additional processing and masking steps, which increase manufacturing costs.
What is needed in the art is a semiconductor device that has an improved bond pad structure that addresses the deficiencies of the above-discussed conventional structure.